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HIP1011
Data Sheet March 2004 FN4311.9
PCI Hot Plug Controller
The HIP1011 is the PCI Hot Plug voltage bus control IC for use in modern computer systems that facilitates hot plugging of adapter cards into and out of an active or passive back plane. Along with discrete power MOSFETs and a few passive components, the HIP1011 creates a small and simple yet complete power control solution. Four independent supplies are controlled, +5V, +3.3V, +12V, and -12V. The +12V and 12V switches are integrated. For the +5V and +3.3V supplies, overcurrent protection is provided by sensing the voltage across external current-sense resistors. For the +12V and -12V supplies, overcurrent protection is provided internally. In addition, an on-chip reference is used to monitor the +5V, +3.3V and +12V outputs for undervoltage conditions. The PWRON input controls the state of the switches. During an overcurrent condition on any output, or an undervoltage condition on the +5V, +3.3V or +12V outputs, all MOSFETs are immediately latched-off and a LOW (0V) is asserted on the FLTN output. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold and turn-on slew rate is provided. A resistor connected to the OCSET pin programs the overcurrent threshold. Capacitors connected to the gate pins set the turn-on rate. Also, a capacitor may be added to the FLTN pin to provide noise immunity.
Features
* Controls Distribution of Four Supplies: +5V, +3.3V, +12V, and -12V * Internal MOSFET Switches for +12V and -12V Outputs * Microprocessor Interface for On/Off Control and Fault Reporting * Adjustable Overcurrent Protection for All Supplies * Provides Fault Isolation * Adjustable Turn-On Slew Rate * Minimum Parts Count Solution * No Charge Pump * Pb-Free Package Options
Applications
* PCI Hot Plug * CompactPCI
Pinout
HIP1011 (SOIC) TOP VIEW
M12VIN FLTN 3V5VG VCC 12VIN 1 2 3 4 5 6 7 8 16 M12VO 15 M12VG 14 12VG 13 GND 12 12VO 11 5VISEN 10 5VS 9 PWRON
Ordering Information
PART NUMBER HIP1011CB HIP1011CB-T HIP1011CBZA (Note) HIP1011CBZA-T (Note) HIP1011EVAL1 TEMP. RANGE (C) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 16 Ld SOIC Tape and Reel 16 Ld SOIC (Pb-free) Tape and Reel (Pb-free) Evaluation Platform M16.15 PKG. DWG. # M16.15
3VISEN 3VS OCSET
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HIP1011 Typical Application
3.3V INPUT 3.3V, 7.6A OUT 5m, 1% 12V, 0.5A OUT -12V, 0.1A OUT 5V, 5A OUT 5m, 1% 5V INPUT HUF761315K8 -12V INPUT HIP1011 M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 6.04k 1% POWER CONTROL INPUT FAULT OUTPUT (ACTIVE LOW) M12VO M12VG 12VG GND 12VO 5VISEN 5VS PWRON 0.033F 0.033F 0.033F
12V INPUT
(OPTIONAL)
NOTE: 1. All capacitors are 10%.
2
HIP1011 Simplified Schematic
5VREF SET (LOW = FAULT) FAULT LATCH LOW = FAULT COMP
FLTN
+ 4.6V
INHIBIT RESET COMP + 2.9V
INHIBIT COMP + 10.8V
INHIBIT VCC VCC COMP + VOCSET/17 + 5VS VCC 3V5VG 5VREF 5VISEN VOCSET/13.3 COMP LOW WHEN VCC < 10V + + 3VS
VCC 5V ZENER REFERENCE
VCC 12VIN POWER-ON RESET
3VISEN
VCC
100A VOCSET OCSET HIGH = FAULT
VCC HIGH = SWITCHES ON PWRON VOCSET/3.3 + + 0.7 M12VG 12VO
COMP GND
3
+ VCC M12VIN
COMP
VOCSET/0.8 + 0.3
12VIN
12VG
M12VIN
M12VO
HIP1011 Pin Descriptions
PIN 1 2 3 4 5 6 7 8 DESIGNATOR M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET FUNCTION -12V Input Fault Output DESCRIPTION -12V Supply Input. Also provides power to the -12V overcurrent circuitry. 5V CMOS Fault Output; LOW = FAULT. An optional capacitor may be place from this pin to ground to provide additional immunity from power supply glitches.
3.3V/5V Gate Output Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the startup ramp. During turn on, this capacitor is charged with a 25A current source. 12V VCC Input 12V Input 3.3V Current Sense 3.3V Source Overcurrent Set Connect to unswitched 12V supply. Switched 12V supply input. Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. Connect to source of 3.3V MOSFET. This connection along with pin 6 (3VISEN) senses the voltage drop across the sense resistor. Connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. All four over current trips can be programmed by changing the value of this resistor. The default (6.04k, 1%) is compatible with the maximum allowable currents as outlined in the PCI specification. Controls all four switches. High to Turn Switches ON, Low to turn them OFF. Connect to source of 5V MOSFET switch. This connection along with pin 11(5VISEN) senses the voltage drop across the sense resistor. Connect to the load side of the current sense resistor in series with source of external 5V MOSFET.
9 10 11 12 13 14
PWRON 5VS 5VISEN 12VO GND 12VG
Power On Control 5V Source 5V Current Sense
Switched 12V Output Switched 12V output. Ground Gate of Internal PMOS Connect to common of power supplies. Connect a capacitor between 12VG and 12VO to set the startup ramp for the +12V supply. This capacitor is charged with a 25A current source during startup. The 3.3V and 5V UV circuitry is enabled after the voltage on 12VG is less than 400mV. Therefore, if the capacitor on the pin 3 (3V5VG) is more than 25% larger than the capacitor on pin 14 (12VG) a false UV may be detected during startup. Connect a capacitor between M12VG and M12VO to set the startup ramp for the M12V supply. This capacitor is charged with 25A during startup. Switched 12V Output.
15 16
M12VG M12VO
Gate of Internal NMOS Switched -12V Output
4
HIP1011
Absolute Maximum Ratings
VCC, 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V12VIN +0.5V 12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0V to +0.5V M12VO, M12VG. . . . . . . . . . . . . . . . . . . . . VM12VIN -0.5V to +0.5V 3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the lesser of VCC or +7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM)
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 125C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Die Characteristics
Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Operating Conditions
VCC Supply Voltage Range. . . . . . . . . . . . . . . . . +10.8V to +13.2V 12V, 5V and 3.3V Input Supply Tolerances . . . . . . . . . . . . . . 10% 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board in free air. See Technical Brief 379 for details. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER 5V/3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Undervoltage Trip Threshold
Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IOC5V VOC5V V5VUV t5VUV
See Figure 1, Typical Application VOCSET = 1.2V
66 4.42 -
7.1 72 4.6 150 6.5 -26 -140 9.0 95 2.86 150 6.5 -26 -140 25.0 280 13 2
79 4.75 350 -20 -110 102 2.97 350 -20 -110 27.5 500 17 -
A mV V ns ms A A A mV V ns ms A A A s s s
5V Undervoltage Fault Response Time 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 5VS Input Bias Current 5VISEN Input Bias Current 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Undervoltage Trip Threshold 3V Undervoltage Fault Response Time 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3VS Input Bias Current 3VISEN Input Bias Current Gate Output Charge Current Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time Gate Turn-Off Time
C3V5VG = 0.022F, C5VOUT = 2000F, RL = 1 IB5VS IB5VISEN IOC3V VOC3V V3VUV t3VUV C3V5VG = 0.022F, C3VOUT = 2000F, RL = 0.43 IB3VS IB3VISEN IC3V5VG tON3V5V tOFF3V5V PWRON = High PWRON = High PWRON = High, V3V5VG = 2V C3V5VG = 0.1F C3V5VG = 0.1F, 3V5VG from 9.5 V to 1V C3V5VG = 0.022F, 3V5VG Falling 90% to 10% PWRON = High PWRON = High See Figure 1, Typical Application VOCSET = 1.2V
-40 -160 88 2.74 -40 -160 22.5 -
5
HIP1011
Electrical Specifications
PARAMETER +12V SUPPLY CONTROL On Resistance of Internal PMOS Overcurrent Threshold 12V Undervoltage Trip Threshold Undervoltage Fault Response Time Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VG = -1V) Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time Turn-Off Time M12VIN Input Bias Current CONTROL I/O PINS Supply Current OCSET Current Overcurrent Fault Response Time PWRON Threshold Voltage FLTN Output Low Voltage FLTN Output High Voltage FLTN Output Latch Threshold 12V Power On Reset Threshold IVCC IOCSET tOC VTHPWRON VFLTN,OL VFLTN,OH VFLTN,TH VPOR,TH VCC Voltage Falling IFLTN = 2mA IFLTN = 0 to -4mA 4 95 0.8 3.9 1.8 9.4 5 100 500 1.6 0.6 4.3 2.3 10 5.8 105 960 2.1 0.9 4.9 3 10.6 mA A ns V V V V V IBM12VIN tOFFM12V rDS(ON)M12 IOCM12V ICM12VG tONM12V PWRON = High, ID = 0.1A, TA = TJ = 25C VOCSET = 1.2V PWRON = High, VM12VG = -4V CM12VG = 0.022F CM12VG = 0.022F, CM12VO = 50F, RL = 120 CM12VG = 0.1F, M12VG CM12VG = 0.022F, M12VG Falling 90% to 10% PWRON = High 0.5 0.30 22.5 0.7 0.37 25 160 16 18 3 2 0.9 0.50 27.5 300 23 2.6 A A s ms s s mA rDS(ON)12 IOC12V V12VUV t12VUV IC12VG tON12V tOFF12V PWRON = High, V12VG = 3V C12VG = 0.022F C12VG = 0.1F, 12VG C12VG = 0.022F, 12VG Rising 10% - 90% PWRON = High, ID = 0.5A, TA = TJ = 25C VOCSET = 1.2V 0.18 1.25 10.5 23.5 .300 1.50 10.8 150 25.0 16 9 3 0.350 1.8 11.15 28.5 20 12 A V ns A ms s s Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70C, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
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HIP1011 Typical Performance Curves
340 1000 4.632 4.631 4.630 4.629 4.628 4.627 260 0 5 600 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 4.626 2.858 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 3.3 UV 2.859 2.860 2.862
PMOS rON +12 (m)
NMOS rON -12 (m)
300 PMOS +12 rON 280
800
700
5V UVTRIP (V)
0
FIGURE 1. rON vs TEMPERATURE
FIGURE 2. UV TRIP vs TEMPERATURE
10.84
100
90 12 UV TRIP (V) OC Vth (mV) 10.83
3V OCVth
80 5V OCVth 70
10.82
10.81
60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
FIGURE 3. 12 UV TRIP vs TEMPERATURE
FIGURE 4. OCVth vs TEMPERATURE (VROCSET = 1.21V)
102
101 IOC SET (A)
100
99
98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
FIGURE 5. OCSET I vs TEMPERATURE
7
3.3V UVTRIP (V)
320
NMOS -12 rON
900
5 UV
2.861
HIP1011 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.053 0.004 0.014 0.007 0.386 0.150 0.228 0.010 0.016 16 0 8 0 MAX 0.069 0.010 0.019 0.010 0.394 0.157 0.244 0.020 0.050 MILLIMETERS MIN 1.35 0.10 0.35 0.19 9.80 3.80 5.80 0.25 0.40 16 8 MAX 1.75 0.25 0.49 0.25 10.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 02/02
L
C D E e H h
C
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS

A1 0.10(0.004)
L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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